/**********************************************************************************
 * SPI_driver.c - Module for using the DSPI on the Kinetis K70 tower module. Only
 * write functionality is available.
 *
 *By Joshua Goertz and Dylan Kleist
 *  Created on: May 15, 2015
 *********************************************************************************/



/**********************************************************************************
* Includes
**********************************************************************************/
#include "includes.h"
#include "SPI_driver.h"

/**********************************************************************************
* DEVICE COMMANDS (MCP4351 Digital Potentiometer 16-Bit mode) INT32U
**********************************************************************************/

/**********************************************************************************
* Public Function Prototypes
**********************************************************************************/
void SPI_Init(INT8U SPInum);
void SPI_Write(INT8U SPInumber, INT32U registerdata);


/**********************************************************************************
* SPI_Init() - Initializes the DSPI modules on the K70. Only 0,1, and 2 are valid
* choices for DSPI initialization
**********************************************************************************/
void SPI_Init(INT8U SPInum){

	if(SPInum == 0){
		//CLK GATING
		SIM_SCGC6 |= SIM_SCGC6_DSPI0_MASK; //Enable module clock
		//PORT SETUP, comment out chip selects that are not being used
		PORTC_PCR1 |= PORT_PCR_MUX(0x2); //PCS3
		PORTC_PCR2 |= PORT_PCR_MUX(0x2); //PCS2
		PORTC_PCR3 |= PORT_PCR_MUX(0x2); //PCS1
		PORTC_PCR4 |= PORT_PCR_MUX(0x2); //PCS0
		PORTC_PCR5 |= PORT_PCR_MUX(0x2); //SCK
		PORTC_PCR6 |= PORT_PCR_MUX(0x2); //SOUT
		PORTC_PCR7 |= PORT_PCR_MUX(0x2); //SIN

		//SPI SETUP
		SPI0_CTAR0 = 0x78420001; //
		SPI0_MCR = 0x803F3C00; //

	}else if(SPInum == 1){
		//CLK GATING
		SIM_SCGC6 |= SIM_SCGC6_DSPI1_MASK; //Enable module clock
		//PORT SETUP
		PORTE_PCR0 |= PORT_PCR_MUX(0x2); //PCS1
		PORTE_PCR1 |= PORT_PCR_MUX(0x2); //SOUT
		PORTE_PCR2 |= PORT_PCR_MUX(0x2); //SCK
		PORTE_PCR3 |= PORT_PCR_MUX(0x2); //SIN
		PORTE_PCR4 |= PORT_PCR_MUX(0x2); //PCS0
		PORTE_PCR5 |= PORT_PCR_MUX(0x2); //PCS2
		PORTE_PCR6 |= PORT_PCR_MUX(0x2); //PCS3

		//SPI SETUP
		SPI1_CTAR0 = 0x78420001; //
		SPI1_MCR = 0x803F3C00; //

	}else if(SPInum == 2){
		//CLK GATING
		SIM_SCGC3 |= SIM_SCGC3_DSPI2_MASK; //Enable module clock
		//PORT SETUP
		PORTB_PCR20 |= PORT_PCR_MUX(0x2); //PCS0 (only available PCS for SPI2)
		PORTB_PCR21 |= PORT_PCR_MUX(0x2); //SCK
		PORTB_PCR22 |= PORT_PCR_MUX(0x2); //SOUT
		PORTB_PCR23 |= PORT_PCR_MUX(0x2); //SIN

		//SPI SETUP
		SPI0_CTAR0 = 0x78420001; //
		SPI0_MCR = 0x803F3C00; //

	}else{		/*do nothing*/
	}

}

/**********************************************************************************
* SPI_Write()
**********************************************************************************/
void SPI_Write(INT8U SPInumber, INT32U registerdata){

	//registerdata |= SPI_PUSHR_EOQ_MASK; //End of que mask, single word write only
	if(SPInumber == 0){
        SPI0_SR &= SPI_SR_TCF_MASK;//Clear the TCF/EOQF
		//SPI0_MCR &= ~SPI_MCR_HALT_MASK; //Enables the SCLK
		SPI0_PUSHR = registerdata;
		while((SPI0_SR & SPI_SR_TCF_MASK) != SPI_SR_TCF_MASK); //Wait to finish
		//SPI0_MCR |= SPI_MCR_HALT_MASK; //Halt the device
		//SPI0_SR &= SPI_SR_TCF_MASK;

	}else if(SPInumber == 1){
		SPI1_PUSHR = registerdata;
		//SPI1_MCR &= ~SPI_MCR_HALT_MASK; //Enables the SCLK
		while((SPI1_SR & SPI_SR_TCF_MASK) != SPI_SR_TCF_MASK); //Wait to finish
		SPI1_MCR |= SPI_MCR_HALT_MASK; //Halt the device
		SPI1_SR &= SPI_SR_TCF_MASK; //Clear the transfer complete flag

	}else if(SPInumber == 2){
		SPI2_PUSHR = registerdata;
		//SPI2_MCR &= ~SPI_MCR_HALT_MASK; //Enables the SCLK
		while((SPI2_SR & SPI_SR_TCF_MASK) != SPI_SR_TCF_MASK); //Wait to finish
		SPI2_MCR |= SPI_MCR_HALT_MASK; //Halt the device
		SPI2_SR &= SPI_SR_TCF_MASK; //Clear the transfer complete flag

	}else{
			/*do nothing*/

		}



}

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